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RF集積回路の設計法 ―5G時代の高周波技術―
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設計技術シリーズ

RF集積回路の設計法―5G時代の高周波技術―

著者： 前多 正氏（芝浦工業大学）
定価： 4,950円（本体4,500円＋税）
判型： A5
ページ数： 354 ページ
ISBN： 978-4-904774- 86-1
発売日： 2020/2/27
管理No： 78

【著者紹介】

【目次】

１．雑音

  1. １－１　抵抗の雑音
  2. １－２　MOSFETの雑音
  3. １－３　熱雑音の分布

２．低雑音増幅器（Low-Noise Amplifier：LNA）

  1. ２－１　受信部構成と受信電力強度
  2. ２－２　雑音指数と入力換算雑音
  3. ２－３　縦列接続構成の受信機の雑音
  4. ２－４　受信信号と雑音レベルの関係
  5. ２－５　入出力整合
  6. ２－６　LNA入力インピーダンスのスミスチャート上の軌跡
  7. ２－７　カスコード構成LNA
  8. ２－８　寄生素子の影響
  9. ２－９　増幅器の出力雑音
  10. ２－10　等雑音円、等利得円
  11. ２－11　回路の非線形性
  12. ２－12　雑音キャンセル型LNA

３．ミキサ（Mixer：MIX）

  1. ３－１　周波数変換の原理
  2. ３－２　イメージ信号
  3. ３－３　イメージ除去ミキサ
  4. ３－４　イメージ除去比
  5. ３－５　位相差π/２（90度）の信号生成回路
    1. ３－５－１　ポリフェーズフィルタ
    2. ３－５－２　フリップフロップを利用した回路
  6. ３－６　ミキサ回路の具体例
    1. ３－６－１　受動ミキサ
    2. ３－６－２　受動ミキサの雑音
    3. ３－６－３　能動ミキサの変換利得
    4. ３－６－４　能動ミキサの雑音
  7. ３－７　ハーモニックリジェクションミキサ
  8. ３－８　最新のミキサ回路

４．電圧制御発振器（Voltage Controlled Oscillator：VCO）

  1. ４－１　LC発振器の発振条件
  2. ４－２　位相雑音
  3. ４－３　その他雑音の経路（アップコンバージョン）及び雑音抑制回路
  4. ４－４　位相雑音が受信動作に及ぼす影響
  5. ４－５　VCOの回路構成例
    1. ４－５－１　n型MOS-VCO
  6. ４－６　直交VCO（Quadrature-VCO）
  7. ４－７　注入同期VCO

５．フェーズロックループ（Phase Locked Loop：PLL）

  1. ５－１　整数分周PLL
    1. ５－１－１　分周器
    2. ５－１－２　位相比較器
    3. ５－１－３　PLL伝達関数とループフィルタ
    4. ５－１－４　PLLループフィルタの実装
    5. ５－１－５　PLLの周波数応答
    6. ５－１－６　雑音源と位相雑音
  2. ５－２　分数分周PLL（fractional-N PLL）
    1. ５－２－１　理想的な分数分周
    2. ５－２－２　シグマデルタ変調器（ΣΔ変調器）と分周比のランダム化
    3. ５－２－３　MASH
    4. ５－２－４　アキュムレータのビット数とスプリアス
    5. ５－２－５　シグマデルタ変調器を用いた分数分周PLL例
    6. ５－２－６　分数分周PLLの伝達関数と位相雑音特性
  3. ５－３　デジタル制御PLL
    1. ５－３－１　デジタル制御発振器
    2. ５－３－２　シグマデルタ変調器
    3. ５－３－３　位相比較
    4. ５－３－４　時間デジタル変換器
    5. ５－３－５　PLL伝達関数とデジタルループフィルタ
    6. ５－３－６　ADPLLの位相雑音

６．アナログベースバンド

  1. ６－１　フィルタ特性とアナログベースバンド信号
  2. ６－２　gmCフィルタ
    1. ６－２－１　単相入力・単相出力gmアンプ
    2. ６－２－２　差動入力gmアンプ
    3. ６－２－３　gmCフィルタ
    4. ６－２－４　代表的なフィルタ特性
    5. ６－２－５　フィルタ特性の自動調整回路
  3. ６－３　離散時間フィルタ
    1. ６－３－１　スイッチトキャパシタを用いた離散処理フィルタ
    2. ６－３－２　デューティ制御離散処理フィルタ
  4. ６－４　ベースバンドアンプ（IFアンプ）

７．受信部全体設計（レベルダイア設計）

  1. ７－１　受信機アーキテクチャ
  2. ７－２　レベルダイア設計
  3. ７－３　アナログ回路の不完全性による復調性能への影響

８．送信部（トランスミッタ）設計

  1. ８－１　トランシーバ全体構成
  2. ８－２　送信機の性能仕様
  3. ８－３　送信機アーキテクチャ
  4. ８－４　送信信号が受信性能に及ぼす影響（SAWフィルタの必要性）
  5. ８－５　低雑音ドライバアンプ回路設計
  6. ８－６　パワーアンプ（Power Amplifier：PA）
  7. ８－７　低歪み・高効率化手法
  8. ８－８　アンテナスイッチ
  9. ８－９　サーキュレータ

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